Análise e simulação de topologias de redes em chip

Abstract

The advance in chips manufacturing have allowed a constant increase in the number of transistors integrated into a single chip. This allows the combination of the components of a computer on a single chip, introducing the Systems on Chip, whose complexity is often increasing with the integration of several components, like processing cores. The communication between these components can be achieved by point-to-point channels, which are more efficient but more expensive, or through multi-point channels, called bus, which are cheaper, but have lower performance. In the upcoming years, the systems on chip tend to be so complex, with hundreds of processing cores, that these communication architectures will become obsolete. Thus it is important to investigate new paradigms of communication so that the message exchange does not become a bottleneck in the performance of systems on chip. An approach which is discussed nowadays is the use of networks on chip, which keep switches to router data packets to their destination and are interconnected according to a specific topology. In this context, this study aims to investigate such networks, analyzing and comparing the performance of networks on chip with Ring, Spidergon, Mesh, Cube Express and Torus topologies, to show the impact that the topology may have on performance and final cost of a network on chip. A semi dynamic routing algorithm for Torus topologies is also introduced.